82NM10 Datasheet, PDF (5/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
Real Time Clock (D31:F0)................................................................................. 129
5.12.1 Update Cycles ...................................................................................... 129
5.12.2 Interrupts ........................................................................................... 130
5.12.3 Lockable RAM Ranges ........................................................................... 130
5.12.4 Century Rollover .................................................................................. 130
5.12.5 Clearing Battery-Backed RTC RAM .......................................................... 131
Processor Interface (D31:F0) ............................................................................ 132
5.13.1 Processor Interface Signals .................................................................... 133
5.13.2 Dual-Processor Issues (Nettop Only) ....................................................... 135
Power Management (D31:F0)............................................................................ 136
5.14.1 Features ............................................................................................. 136
5.14.2 Chipset and System Power States........................................................... 137
5.14.3 System Power Planes ............................................................................ 139
5.14.4 SMI#/SCI Generation ........................................................................... 140
5.14.5 Dynamic Processor Clock Control ............................................................ 142
5.14.6 Dynamic PCI Clock Control (Netbook Only) .............................................. 145
5.14.7 Sleep States ........................................................................................ 147
5.14.8 Thermal Management ........................................................................... 150
5.14.9 Event Input Signals and Their Usage ....................................................... 152
5.14.10ALT Access Mode .................................................................................. 155
5.14.11System Power Supplies, Planes, and Signals ............................................ 158
5.14.12Clock Generators.................................................................................. 161
5.14.13Legacy Power Management Theory of Operation ....................................... 162
System Management (D31:F0).......................................................................... 163
5.15.1 Theory of Operation.............................................................................. 163
5.15.2 Heartbeat and Event Reporting via SMBus ............................................... 164
SATA Host Controller (D31:F2).......................................................................... 168
5.16.1 Theory of Operation.............................................................................. 170
5.16.2 SATA Swap Bay Support........................................................................ 171
5.16.3 Power Management Operation................................................................ 171
5.16.4 SATA LED............................................................................................ 173
5.16.5 AHCI Operation .................................................................................... 173
High Precision Event Timers .............................................................................. 174
5.17.1 Timer Accuracy .................................................................................... 174
5.17.2 Interrupt Mapping ................................................................................ 175
5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 175
5.17.4 Enabling the Timers .............................................................................. 176
5.17.5 Interrupt Levels ................................................................................... 176
5.17.6 Handling Interrupts .............................................................................. 176
5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 177
USB UHCI Host Controllers (D29:F0, F1, F2, and F3)............................................ 177
5.18.1 Data Structures in Main Memory............................................................. 177
5.18.2 Data Transfers to/from Main Memory ...................................................... 178
5.18.3 Data Encoding and Bit Stuffing ............................................................... 178
5.18.4 Bus Protocol ........................................................................................ 178
5.18.5 Packet Formats .................................................................................... 179
5.18.6 USB Interrupts..................................................................................... 179
5.18.7 USB Power Management ....................................................................... 182
5.18.8 USB Legacy Keyboard Operation............................................................. 182
USB EHCI Host Controller (D29:F7) ................................................................... 185
5.19.1 EHC Initialization.................................................................................. 185
5.19.2 Data Structures in Main Memory............................................................. 186
5.19.3 USB 2.0 Enhanced Host Controller DMA ................................................... 186
Datasheet
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