82NM10 Datasheet, PDF (470/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Table 15-135.SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 2 of 2)
Offset Mnemonic
Register Name
40h–41h IDE_TIMP Primary IDE Timing
42h–43h IDE_TIMS Secondary IDE Timing
44h
SIDETIM Slave IDE Timing
48h
SDMA_CNT Synchronous DMA Control
4Ah–4Bh SDMA_TIM Synchronous DMA Timing
54h–57h IDE_CONFIG IDE I/O Configuration
70h–71h
PID
PCI Power Management Capability ID
72h–73h
74h–75h
80h–81h
82h–83h
84h–87h
88h–89h
90h
92h–93h
PC
PMCS
MSICI
MSIMC
MSIMA
MSIMD
MAP
PCS
PCI Power Management Capabilities
PCI Power Management Control and
Status
Message Signaled Interrupt Capability
ID
Message Signaled Interrupt Message
Control
Message Signaled Interrupt Message
Address
Message Signaled Interrupt Message
Data
Address Map
Port Control and Status
94h–97h
A0h
A4h
A8h–ABh
ACh–AFh
C0h
C4h
D0h–D3h
E0h–E3h
E4h–E7h
E8h–EBh
SIR
SIRI
STRD
SCAP0
SCAP1
ATC
ATS
SP
BFCS
BFTD1
BFTD2
SATA Initialization Register
SATA Indexed Registers Index
SATA Indexed Register Data
SATA Capability Register 0
SATA Capability Register 1
APM Trapping Control
ATM Trapping Status
Scratch Pad
BIST FIS Control/Status
BIST FIS Transmit Data, DW1
BIST FIS Transmit Data, DW2
Default
0000h
0000h
00h
00h
0000h
00000000h
See register
description
4002h
0000h
7005h
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
R/W, RO,
R/WC
RO
0000h
RO, R/W
00000000h RO, R/W
0000h
R/W
00h
0000h
00000000h
00h
XXXXXXXXh
00100012h
00000048h
00h
00h
00000000h
00000000h
00000000h
00000000h
R/W
R/W, RO,
R/WC
R/W
R/W
R/W
RO
RO
R/W
R/WC
R/W
R/W, R/WC
R/W
R/W
NOTE: The Chipset SATA controller is not arbitrated as a PCI device; therefore, it does not need a
master latency timer.
470
Datasheet