82NM10 Datasheet, PDF (79/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-30.Type 1 Address Format
Bits
7:2
1
0
Definition
Register (same as the PCI Local Bus Specification)
0
Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.
Note:
Chipset USB controllers cannot perform peer-to-peer traffic.
5.1.6
Note:
PCI-to-PCI Bridge Model
From a software perspective, chipset contains a PCI-to-PCI bridge. This bridge connects
DMI to the PCI bus. By using the PCI-to-PCI bridge software model, Chipset can have
its decode ranges programmed by existing plug-and-play software such that PCI ranges
do not conflict with graphics aperture ranges in the Host controller.
All downstream devices should be disabled before reconfiguring the PCI Bridge. Failure
to do so may cause undefined results.
5.1.7 IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), Chipset asserts
one address signal as an IDSEL. When accessing device 0, Chipset asserts AD16. When
accessing Device 1, Chipset asserts AD17. This mapping continues all the way up to
device 15 where Chipset asserts AD31. Note that Chipset internal functions (Intel HD
Audio, USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI
bus (DMI) from the external PCI bus. The integrated LAN controller is Device 8 on
chipset’s PCI bus, and hence it uses AD24 for IDSEL.
5.1.8
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to
contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus
cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration
space is supported by a mapping mechanism implemented within Chipset. The PCI
Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration
space, Mechanism 1 and Mechanism 2. Chipset only supports Mechanism 1.
Warning: Configuration writes to internal devices, when the devices are disabled, are invalid and
may cause undefined results.
Datasheet
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