82NM10 Datasheet, PDF (149/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.14.9
5.14.9.1
Note:
Event Input Signals and Their Usage
Chipset has various input signals that trigger specific events. This section describes
those signals and how they should be used.
PWRBTN# (Power Button)
Chipset PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16
ms de-bounce on the input. The state transition descriptions are included in Table 5-62.
Note that the transitions start as soon as the PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the Power Button is released.
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. Refer to Power Button Override
Function section below for further detail.
Table 5-62.Transitions Due to Power Button
Present
State
S0/Cx
Event
PWRBTN# goes low
S1–S5 PWRBTN# goes low
G3
PWRBTN# pressed
Transition/Action
SMI# or SCI generated
(depending on SCI_EN)
Wake Event. Transitions to
S0 state
None
S0–S4
PWRBTN# held low
for at least 4
consecutive seconds
Unconditional transition to
S5 state
Comment
Software typically initiates a
Sleep state
Standard wakeup
No effect since no power
Not latched nor detected
No dependence on processor
(e.g., Stop-Grant cycles) or
any other subsystem
Note:
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–
S4), even if PWROK is not active. In this case, the transition to the G2/S5 state should
not depend on any particular response from the processor (e.g., a Stop-Grant cycle),
nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable via the
PWRBTN_LVL bit.
The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when Chipset is in a S0 state. If the
PWRBTN# signal is asserted and held active when the system is in a suspend state
(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0
state, the 4-second timer starts.
Datasheet
149