82NM10 Datasheet, PDF (667/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Serial Peripheral Interface (SPI)
2 Atomic Cycle Sequence (ACS) — R/W.
0 = No atomic cycle sequence.
1 = When set to 1 along with the SCGO assertion, the Chipset will execute a sequence
of commands on the SPI interface without allowing the LAN component to arbitrate
and interleave cycles.
1 SPI Cycle Go (SCGO) — R/W. This bit always returns 0 on reads.
0 = SPI cycle Not started.
1 = A write to this register with a 1 in this bit starts the SPI cycle defined by the other
bits of this register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action.
NOTE: Writes to this bit while the Cycle In Progress bit is set are ignored.
NOTE: Other bits in this register can be programmed for the same transaction when
writing this bit to 1.
0 SPI Access Request — R/W. This bit is used by software to request that the other SPI
master stop initiating long transactions on the SPI bus.
0 = No request.
1 = Request that the other SPI master stop initiating long transactions on the SPI bus.
NOTE: This bit defaults to a 1 and must be cleared by BIOS after completing the
accesses for the boot process.
21.1.3
SPIA—SPI Address Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 04h
Attribute:
R/W
Default Value:
00000000hSize:32 bits
Bit
Description
31:24 Reserved
23:0 SPI Cycle Address (SCA) — R/W. This field is shifted out as the SPI Address (MSb
first). Bits 23:0 correspond to Address bits 23:0.
Datasheet
667