82NM10 Datasheet, PDF (443/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.9.9
TCO_WDCNT—TCO Watchdog Control Register
Offset Address: TCOBASE + 0Eh
Default Value: 00h
Power Well:
Resume
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 Watchdog Status (WDSTATUS) — R/W. The value written to this register will be
sent in the Alert On LAN message on the SMLINK interface. It can be used by the BIOS
or system management software to indicate more details on the boot progress. This
register will be reset to the default of 00h based on RSMRST# (but not PCI reset).
13.9.10 SW_IRQ_GEN—Software IRQ Generation Register
Offset Address: TCOBASE + 10h
Default Value: 11h
Power Well:
Core
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved
1 IRQ12_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ12 signal as
received by the chipset’s SERIRQ logic. This bit must be a 1 (default) if the Chipset is
expected to receive IRQ12 assertions from a SERIRQ device.
0 IRQ1_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ1 signal as
received by the chipset’s SERIRQ logic. This bit must be a 1 (default) if the Chipset is
expected to receive IRQ1 assertions from a SERIRQ device.
13.9.11 TCO_TMR—TCO Timer Initial Value Register
I/O Address:
Default Value:
Lockable:
TCOBASE +12h
0004h
No
Attribute:
Size:
Power Well:
R/W
16-bit
Core
Bit
Description
15:10 Reserved
9:0 TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the
TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not
be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows
timeouts ranging from 1.2 second to 613.8 seconds. Note: The timer has an error of
± 1 tick (0.6s).
The TCO Timer will only count down in the S0 state.
Datasheet
443