82NM10 Datasheet, PDF (509/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
31:28
Interface Communication Control (ICC) — R/W. This is a four bit field which can be used to control
reset and power states of the interface. Writes to this field will cause actions on the interface, either as
primitives or an OOB sequence, and the resulting status of the interface will be reported in the PxSSTS
register (Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3:
ABAR+2A4h).
Value
Fh–7h
6h
5h–3h
2h
1h
0h
Definition
Reserved
Slumber: This will cause the Chipset to request a transition of the interface to the
slumber state. The SATA device may reject the request and the interface will remain
in its current state
Reserved
Partial: This will cause the Chipset to request a transition of the interface to the partial
state. The SATA device may reject the request and the interface will remain in its
current state.
Active: This will cause the Chipset to request a transition of the interface into the
active
No-Op / Idle: When software reads this value, it indicates the Chipset is not in the
process of changing the interface state or sending a device reset, and a new link
command may be issued.
When system software writes a non-reserved value other than No-Op (0h), the Chipset will perform the
action and update this field back to Idle (0h).
If software writes to this field to change the state to a state the link is already in (e.g. interface is in the
active state and a request is made to go to the active state), the Chipset will take no action and return
this field to Idle.
NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to 02h or 06h.
27 Aggressive Slumber / Partial (ASP) — R/W. When set, and the ALPE bit (bit 26) is set, the Chipset
will aggressively enter the slumber state when it clears the PxCI register and the PxSACT register is
cleared. When cleared, and the ALPE bit is set, the Chipset will aggressively enter the partial state
when it clears the PxCI register and the PxSACT register is cleared.
26 Aggressive Link Power Management Enable (ALPE) — R/W. When set, the Chipset will
aggressively enter a lower link power state (partial or slumber) based upon the setting of the ASP bit
(bit 27).
25 Drive LED on ATAPI Enable (DLAE) — R/W. When set, the Chipset will drive the LED pin active for
ATAPI commands (PxCLB[CHz.A] set) in addition to ATA commands. When cleared, the Chipset will only
drive the LED pin active for ATA commands. See Section 5.17.5 - Volume 1 for details on the activity
LED.
24 HDevice is ATAPI (ATAPI) — R/W. When set, the connected device is an ATAPI device. This bit is
used by the Chipset to control whether or not to generate the Nettop LED when commands are active.
See Section 5.17.5 - Volume 1 for details on the activity LED.
23:20 Reserved
Datasheet
509