82NM10 Datasheet, PDF (592/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.1.49 L1ADDU—Link 1 Upper Address Register
(Intel HD Audio Controller—D27:F0)
Address Offset: 14Ch–14Fh
Default Value: 00000000h
Attribute:
Size:
Bit
Description
31:0 Link 1 Upper Address — RO. Hardwired to 00000000h.
RO
32 bits
18.2
Intel HD Audio Memory-Mapped Configuration
Registers
(Intel HD Audio— D27:F0)
The base memory location for these memory mapped configuration registers is
specified in the HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The
individual registers are then accessible at HDBAR + Offset as indicated in the following
table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Table 18-147.Intel HD Audio PCI Register Address Map
(Intel HD Audio D27:F0) (Sheet 1 of 5)
HDBAR +
Offset
Mnemonic
Register Name
00h–01h
02h
03h
04h–05h
06h–07h
08h–0Bh
0Ch–0Dh
0Eh–0Fh
10h–11h
12h–13h
14h–17h
1 8h–19h
1Ah–1Bh
1Ch–1Fh
20h–23h
24h–27h
30h–33h
34h–37h
40h–43h
GCAP
Global Capabilities
VMIN
Minor Version
VMAJ
Major Version
OUTPAY Output Payload Capability
INPAY
Input Payload Capability
GCTL
Global Control
WAKEEN Wake Enable
STATESTS State Change Status
GSTS
Global Status
—
Reserved
—
Reserved
OUTSTRMPAY Output Stream Payload Capability
INSTRMPAY Input Stream Payload Capability
—
Reserved
INTCTL
Interrupt Control
INTSTS
Interrupt Status
WALCLK Wall Clock Counter
SSYNC
Stream Synchronization
CORBLBASE CORB Lower Base Address
Default
Access
4401h
00h
01h
003Ch
001Dh
00000000h
0000h
0000h
0000h
0000h
00000000h
0030h
0018h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
RO
RO
RO
RO
RO
R/W
R/W
R/WC
R/WC
RO
RO
RO
RO
RO
R/W
RO
RO
R/W
R/W, RO
592
Datasheet