82NM10 Datasheet, PDF (27/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Table 5-71 Legacy Replacement Routing ................................................................. 175
Table 5-72 Bits Maintained in Low Power States ....................................................... 182
Table 5-73 USB Legacy Keyboard State Transitions................................................... 184
Table 5-74 UHCI vs. EHCI ..................................................................................... 185
Table 5-75 Debug Port Behavior ............................................................................. 194
Table 5-76 I²C Block Read..................................................................................... 203
Table 5-77 Enable for SMBALERT# ......................................................................... 206
Table 5-78 Enables for SMBus Slave Write and SMBus Host Events ............................. 206
Table 5-79 Enables for the Host Notify Command ..................................................... 206
Table 5-80 Slave Write Registers ............................................................................ 208
Table 5-81 Command Types .................................................................................. 209
Table 5-82 Read Cycle Format ............................................................................... 210
Table 5-83 Data Values for Slave Read Registers ...................................................... 210
Table 5-84 Host Notify Format ............................................................................... 212
Table 5-85 SPI Implementation Options .................................................................. 214
Table 5-86 Required Commands and Opcodes .......................................................... 215
Table 5-87 Chipset Standard SPI Commands ........................................................... 215
Table 5-88 Flash Protection Mechanism Summary..................................................... 216
Table 6-89 Chipset Ballout by Signal Name .............................................................. 221
Table 8-90 Chipset Absolute Maximum Ratings........................................................ 227
Table 8-91 DC Current Characteristics..................................................................... 228
Table 8-92 DC Characteristic Input Signal Association ............................................... 228
Table 8-93 DC Input Characteristics........................................................................ 229
Table 8-94 DC Characteristic Output Signal Association ............................................. 231
Table 8-95 DC Output Characteristics...................................................................... 232
Table 8-96 Other DC Characteristics ....................................................................... 234
Table 8-97 Clock Timings ...................................................................................... 235
Table 8-98 SATA Interface Timings ......................................................................... 236
Table 8-99 SMBus Timing ...................................................................................... 236
Table 8-100 Intel HD Audio Timing ........................................................................... 237
Table 8-101 LPC Timing .......................................................................................... 237
Table 8-102 Miscellaneous Timings........................................................................... 238
Table 8-103 SPI Timings ......................................................................................... 238
Table 8-104 (Power Sequencing and Reset Signal Timings ........................................... 238
Table 8-105 Power Management Timings................................................................... 240
Table 9-106 PCI Devices and Functions ..................................................................... 259
Table 9-107 Fixed I/O Ranges Decoded by Chipset ..................................................... 260
Table 9-108 Variable I/O Decode Ranges .................................................................. 263
Table 9-109 Memory Decode Ranges from Processor Perspective.................................. 264
Table 10-110 Chipset Configuration Register Memory Map (Memory Space)..................... 267
Table 11-111 LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0) ......... 302
Table 11-112 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ........ 309
Table 11-113 Data Register Structure......................................................................... 313
Table 11-114 Chipset Integrated LAN Controller CSR Space Register Address Map ............ 313
Table 11-115 Self-Test Results Format ....................................................................... 319
Table 11-116 Statistical Counters............................................................................... 326
Table 11-117 ASF Register Address Map ..................................................................... 328
Table 12-118 PCI Bridge Register Address Map (PCI-PCI—D30:F0) ................................. 342
Table 13-119 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) ........................ 358
Table 13-120 DMA Registers ..................................................................................... 377
Table 13-121 PIC Registers (LPC I/F—D31:F0)............................................................. 387
Table 13-122 APIC Direct Registers (LPC I/F—D31:F0) ................................................. 394
Table 13-123 APIC Indirect Registers (LPC I/F—D31:F0) ............................................... 394
Datasheet
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