82NM10 Datasheet, PDF (420/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.8.3.4
13.8.3.5
Bit
Description
1
(Nettop
Only)
Reserved
1
(Netbook
Only)
Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This
bit is reset to 0 by PLTRST#
0 = Bus master requests will not cause a break from the C3 state.
1 = Enable Bus Master requests (internal, external or BM_BUSY#) to cause a break
from the C3 state.
If software fails to set this bit before going to C3 state, the Chipset on Netbook
platform will still return to a snoopable state from C3 or C4 states due to bus master
activity.
0
SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for
various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in
GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
PM1_TMR—Power Management 1 Timer Register
I/O Address:
PMBASE + 08h
(ACPI PMTMR_BLK)
Default Value:
Lockable:
Power Well:
xx000000h
No
Core
Attribute:
Size:
Usage:
RO
32-bit
ACPI
Bit
Description
31:24 Reserved
23:0
Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This
counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0
during a PCI reset, and then continues counting as long as the system is in the S0
state. After an S1 state, the counter will not be reset (it will continue counting from the
last value in S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the
TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur
every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI
interrupt is also generated.
PROC_CNT—Processor Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 10h
(ACPI P_BLK)
Attribute:
00000000h
Size:
No (bits 7:5 are write once)Usage:
Core
Bit
Description
31:18 Reserved
R/W, RO, WO
32-bit
ACPI or Legacy
420
Datasheet