82NM10 Datasheet, PDF (12/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

13.2
13.3
13.4
13.5
13.1.32FDVER—Feature Detection Version
(LPC I/F—D31:F0) ................................................................................ 376
13.1.33FDVCT—Feature Vector Register (LPC I/F—D31:F0)................................... 376
13.1.34RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0) ................................................................................ 376
DMA I/O Registers (LPC I/F—D31:F0)................................................................. 377
13.2.1 DMABASE_CA—DMA Base and Current Address
Registers (LPC I/F—D31:F0)................................................................... 378
13.2.2 DMABASE_CC—DMA Base and Current Count Registers
(LPC I/F—D31:F0) ................................................................................ 378
13.2.3 DMAMEM_LP—DMA Memory Low Page Registers
(LPC I/F—D31:F0) ................................................................................ 379
13.2.4 DMACMD—DMA Command Register (LPC I/F—D31:F0) .............................. 379
13.2.5 DMASTA—DMA Status Register (LPC I/F—D31:F0) .................................... 380
13.2.6 DMA_WRSMSK—DMA Write Single Mask Register
(LPC I/F—D31:F0) ................................................................................ 380
13.2.7 DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0) ................................................................................ 381
13.2.8 DMA Clear Byte Pointer Register (LPC I/F—D31:F0)................................... 382
13.2.9 DMA Master Clear Register (LPC I/F—D31:F0) .......................................... 382
13.2.10DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0) ........................ 382
13.2.11DMA_WRMSK—DMA Write All Mask Register
(LPC I/F—D31:F0) ................................................................................ 383
Timer I/O Registers (LPC I/F—D31:F0) ............................................................... 383
13.3.1 TCW—Timer Control Word Register (LPC I/F—D31:F0) ............................... 384
13.3.2 RDBK_CMD—Read Back Command (LPC I/F—D31:F0) ............................... 385
13.3.3 LTCH_CMD—Counter Latch Command (LPC I/F—D31:F0) ........................... 385
13.3.4 SBYTE_FMT—Interval Timer Status Byte Format Register
(LPC I/F—D31:F0) ................................................................................ 386
13.3.5 Counter Access Ports Register (LPC I/F—D31:F0) ...................................... 387
8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0) ........................................................................................... 387
13.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0) ........................................ 387
13.4.2 ICW1—Initialization Command Word 1 Register
(LPC I/F—D31:F0) ................................................................................ 388
13.4.3 ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0) ................................................................................ 389
13.4.4 ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0) ......................................................... 390
13.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0) ......................................................... 390
13.4.6 ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0) ................................................................................ 390
13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0) .................................................................... 391
13.4.8 OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0) ................................................................................ 391
13.4.9 OCW3—Operational Control Word 3 Register
(LPC I/F—D31:F0) ................................................................................ 392
13.4.10ELCR1—Master Controller Edge/Level Triggered Register
(LPC I/F—D31:F0) ................................................................................ 393
13.4.11ELCR2—Slave Controller Edge/Level Triggered Register
(LPC I/F—D31:F0) ................................................................................ 393
Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................ 394
13.5.1 APIC Register Map (LPC I/F—D31:F0)...................................................... 394
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