|
82NM10 Datasheet, PDF (281/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
|
◁ |
Chipset Configuration Registers
10.1.35 IOTRn â I/O Trap Register (0-3)
Offset Address:
Default Value:
1E80â1E87h Register 0
1E88â1E8Fh Register 1
1E90â1E97h Register 2
1E98â1E9Fh Register 3
0000000000000000h
Attribute:
Size:
R/W, RO
64-bit
These registers are used to specify the set of I/O cycles to be trapped and to enable
this functionality.
Bit
63:50
49
48
47:40
39:36
35:32
31:24
23:18
17:16
15:2
1
0
Description
Reserved
Read/Write Mask (RWM) â R/W.
0 = The cycle must match the type specified in bit 48.
1 = Trapping logic will operate on both read and write cycles.
Read/Write# (RWIO) â R/W.
0 = Write
1 = Read
NOTE: The value in this field does not matter if bit 49 is set.
Reserved
Byte Enable Mask (BEM) â R/W. A 1 in any bit position indicates that any value in
the corresponding byte enable bit in a received cycle will be treated as a match. The
corresponding bit in the Byte Enables field, below, is ignored.
Byte Enables (TBE) â R/W. Active-high DWord-aligned byte enables.
Reserved
Address[7:2] Mask (ADMA) â R/W. A 1 in any bit position indicates that any value
in the corresponding address bit in a received cycle will be treated as a match. The
corresponding bit in the Address field, below, is ignored. The mask is only provided
for the lower 6 bits of the DWord address, allowing for traps on address ranges up to
256 bytes in size.
Reserved
I/O Address[15:2] (IOAD) â R/W. DWord-aligned address
Reserved
Trap and SMI# Enable (TRSE) â R/W.
0 = Trapping and SMI# logic disabled.
1 = The trapping logic specified in this register is enabled.
Datasheet
281
|
▷ |