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82NM10 Datasheet, PDF (168/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset
Functional Description
5.16.2
Note:
SATA Swap Bay Support
Dynamic Hot-Plug (e.g., surprise removal) is not supported by the SATA host controller
without special support from AHCI and the proper board hardware. However, Chipset
does provide for basic SATA swap bay support using the PSC register configuration bits
and power management flows. A device can be powered down by software and the port
can then be disabled, allowing removal and insertion of a new device.
This SATA swap bay operation requires board hardware (implementation specific),
BIOS, and operating system support.
5.16.3
Power Management Operation
Power management of Chipset SATA controller and ports will cover operations of the
host controller and the SATA wire.
5.16.3.1
Power State Mappings
The D0 PCI power management state for device is supported by Chipset SATA
controller.
SATA devices may also have multiple power states. From parallel ATA, three device
states are supported through ACPI. They are:
• D0 – Device is working and instantly available.
• D1 – device enters when it receives a STANDBY IMMEDIATE command. Exit latency
from this state is in seconds
• D3 – from the SATA device’s perspective, no different than a D1 state, in that it is
entered via the STANDBY IMMEDIATE command. However, an ACPI method is also
called which will reset the device and then cut its power.
Each of these device states are subsets of the host controller’s D0 state.
Finally, SATA defines three PHY layer power states, which have no equivalent mappings
to parallel ATA. They are:
• PHY READY – PHY logic and PLL are both on and active
• Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer
than 10 ns
• Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to
10 ms.
Since these states have much lower exit latency than the ACPI D1 and D3 states, the
SATA controller defines these states as sub-states of the device D0 state.
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Datasheet