82NM10 Datasheet, PDF (543/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
16.2.2.4
Bit
Description
4 Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Host System Error Status bit
(D29:F7:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt. The interrupt is acknowledged by software
clearing the Host System Error bit.
3 Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F7:CAPLENGTH +
24h, bit 3) in the USB2.0_STS register is a 1, the host controller will issue an
interrupt. The interrupt is acknowledged by software clearing the Frame List
Rollover bit.
2 Port Change Interrupt Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F7:CAPLENGTH +
24h, bit 2) in the USB2.0_STS register is a 1, the host controller will issue an
interrupt. The interrupt is acknowledged by software clearing the Port Change
Detect bit.
1 USB Error Interrupt Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F7:CAPLENGTH + 24h,
bit 1) in the USB2.0_STS register is a 1, the host controller will issue an interrupt
at the next interrupt threshold. The interrupt is acknowledged by software by
clearing the USBERRINT bit in the USB2.0_STS register.
0 USB Interrupt Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the USBINT bit (D29:F7:CAPLENGTH + 24h, bit 0)
in the USB2.0_STS register is a 1, the host controller will issue an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software by clearing the
USBINT bit in the USB2.0_STS register.
FRINDEX—Frame Index Register
Offset:
MEM_BASE + 2Ch–2Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
The SOF frame number value for the bus SOF token is derived or alternatively managed
from this register. Refer to Section 4 of the EHCI specification for a detailed explanation
of the SOF value management requirements on the host controller. The value of
FRINDEX must be within 125 µs
(1 micro-frame) ahead of the SOF token value. The SOF value may be implemented as
an 11-bit shadow register. For this discussion, this shadow register is 11 bits and is
named SOFV. SOFV updates every 8 micro-frames. (1 millisecond). An example
implementation to achieve this behavior is to increment SOFV each time the
FRINDEX[2:0] increments from 0 to 1.
Software must use the value of FRINDEX to derive the current micro-frame number,
both for
high-speed isochronous scheduling purposes and to provide the get micro-frame
number function required to client drivers. Therefore, the value of FRINDEX and the
Datasheet
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