82NM10 Datasheet, PDF (569/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.2.15 SLV_STS—Slave Status Register (SMBUS—D31:F3)
Note:
Register Offset: SMBASE + 10h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
Bit
Description
7:1 Reserved
0 HOST_NOTIFY_STS — R/WC. The Chipset sets this bit to a 1 when it has completely
received a successful Host Notify Command on the SMLink pins. Software reads this bit
to determine that the source of the interrupt or SMI# was the reception of the Host
Notify Command. Software clears this bit after reading any information needed from
the Notify address and data registers by writing a 1 to this bit. Note that the Chipset
will allow the Notify Address and Data registers to be over-written once this bit has
been cleared. When this bit is 1, the Chipset will NACK the first byte (host address) of
any new “Host Notify” commands on the SMLink. Writing a 0 to this bit has no effect.
17.2.16 SLV_CMD—Slave Command Register (SMBUS—D31:F3)
Register Offset: SMBASE + 11h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:2 Reserved
2 SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the
SMBALERT# source. This bit is logically inverted and ANDed with the
SMBALERT_STS bit (offset SMBASE + 00h, bit 5). The resulting signal is distributed
to the SMI# and/or interrupt generation logic. This bit does not effect the wake
logic.
1 HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a
Host Notify command as a wake event. When enabled this event is “OR”ed in with the
other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General
Purpose Event 0 Status register.
0 = Disable
1 = Enable
Datasheet
569