82NM10 Datasheet, PDF (292/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.47 OIC—Other Interrupt Control Register
Offset Address: 31FF–31FFh
Default Value: 00h
Attribute:
Size:
R/W
8-bit
Bit
Description
7:2 Reserved
1
Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Chipset generates IRQ13 internally and holds it until an I/O
port F0h write. It will also drive IGNNE# active.
0
APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
10.1.48 RC—RTC Configuration Register
Offset Address: 3400–3403h
Default Value: 00000000h
Attribute:
Size:
R/W, R/WLO
32-bit
Bit
Description
31:5
4
3
2
1:0
Reserved
Upper 128 Byte Lock (UL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return valid data. This bit is
reset on system reset.
Lower 128 Byte Lock (LL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return valid data. Bit reset on
system reset.
Upper 128 Byte Enable (UE) — R/W.
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
Reserved
292
Datasheet