82NM10 Datasheet, PDF (641/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.35 MID—Message Signaled Interrupt Identifiers Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 80h–81h
Default Value: 9005h
Attribute:
Size:
RO
16 bits
Bit
Description
15:8
7:0
Next Pointer (NEXT) — RO. This field indicates the location of the next pointer in the
list.
Capability ID (CID) — RO. Capabilities ID indicates MSI.
19.1.36 MC—Message Signaled Interrupt Message Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 82–83h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:8
7
6:4
3:1
0
Reserved
64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.
Multiple Message Enable (MME) — R/W. These bits are R/W for software
compatibility, but only one message is ever sent by the root port.
Multiple Message Capable (MMC) — RO. Only one message is required.
MSI Enable (MSIE) — R/W.
0 = Disabled.
1 = Enabled and traditional interrupt pins are not used to generate interrupts.
NOTE: CMD.BME (D28:F0/F1/F2/F3:04h:bit 2) must be set for an MSI to be generated.
If CMD.BME is cleared, and this bit is set, no interrupts (not even pin based) are
generated.
19.1.37 MA—Message Signaled Interrupt Message Address
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset: 84h–87h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:2
1:0
Address (ADDR) — R/W. This field contains the lower 32 bits of the system specified
message address; always DWord aligned.
Reserved
Datasheet
641