82NM10 Datasheet, PDF (206/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
NOTE: The external microcontroller is responsible to make sure that it does not update the
contents of the data byte registers until they have been read by the system processor.
Chipset overwrites the old value with any new value received. A race condition is possible
where the new value is being written to the register just at the time it is being read.
Chipset will not attempt to cover this race condition (i.e., unpredictable results in this
case).
Table 5-81.Command Types
Command
Type
Description
0
1
2
3
4
5
6
7
8
9–FFh
Reserved
WAKE/SMI#. This command wakes the system if it is not already awake. If
system is already awake, an SMI# is generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is
already awake. The SMI handler should then clear this bit.
Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and
has the same effect as the Powerbutton Override occurring.
HARD RESET WITHOUT CYCLING: This command causes a hard reset of the
system (does not include cycling of the power supply). This is equivalent to a write
to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0.
HARD RESET SYSTEM. This command causes a hard reset of the system
(including cycling of the power supply). This is equivalent to a write to the CF9h
register with bits 3:1 set to 1.
Disable the TCO Messages. This command will disable Chipset from sending
Heartbeat and Event messages (as described in Section 5.15.2). Once this
command has been executed, Heartbeat and Event message reporting can only be
re-enabled by assertion and deassertion of the RSMRST# signal.
WD RELOAD: Reload watchdog timer.
Reserved
SMLINK_SLV_SMI. When Chipset detects this command type while in the S0
state, it sets the SMLINK_SLV_SMI_STS bit (see Section 13.9.5). This command
should only be used if the system is in an S0 state. If the message is received
during S1–S5 states, Chipset acknowledges it, but the SMLINK_SLV_SMI_STS bit
does not get set.
Note: It is possible that the system transitions out of the S0 state at the same time
that the SMLINK_SLV_SMI command is received. In this case, the
SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to
sleep. Once the system returns to S0, the SMI associated with this bit would then
be generated. Software must be able to handle this scenario.
Reserved
206
Datasheet