82NM10 Datasheet, PDF (78/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
• When an address parity error is detected on PCI, the PCI bridge will not claim the
cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle
should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept
of address parity error, so claiming the cycle could result in the rest of the system
seeing a bad transaction as a good transaction.
5.1.4
PCIRST#
The PCIRST# pin is generated under two conditions:
• PLTRST# active
• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1
The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but
not other agents in the system.
5.1.5
Peer Cycles
The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and
configuration cycle types. Peer cycles are only allowed through VC0, and are enabled
with the following bits:
• BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Memory and IO cycles
• BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles
When enabled for peer for one of the above cycle types, the PCI bridge will perform a
peer decode to see if a peer agent can receive the cycle. When not enabled, memory
cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles
are not claimed.
Configuration cycles have special considerations. Under the PCI Local Bus Specification,
these cycles are not allowed to be forwarded upstream through a bridge. However, to
enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are
allowed into the part. The address format of the type 1 cycle is slightly different from a
standard PCI configuration cycle to allow addressing of extended PCI space. The format
is as follows:
Table 5-30.Type 1 Address Format
Bits
Definition
31:27
26:24
23:16
15:11
10:8
Reserved (same as the PCI Local Bus Specification)
Extended Configuration Address – allows addressing of up to 4K. These
bits are combined with bits 7:2 to get the full register.
Bus Number (same as the PCI Local Bus Specification)
Device Number (same as the PCI Local Bus Specification)
Function Number (same as the PCI Local Bus Specification)
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Datasheet