82NM10 Datasheet, PDF (120/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts
on a PCI board to share a single line across the connector. When a PIRQx# is routed to
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
sensitive mode. Chipset internally inverts the PIRQx# line to send an active high level
to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer
be used by an active high device (through SERIRQ). However, active low interrupts can
share their interrupt with PCI interrupts.
Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external
PIRQ to be asserted. Chipset receives the PIRQ input, like all of the other external
sources, and routes it accordingly.
5.10
Advanced Programmable Interrupt Controller
(APIC) (D31:F0)
In addition to the standard ISA-compatible PIC described in the previous chapter,
Chipset incorporates the APIC. While the standard interrupt controller is intended for
use in a uni-processor system, APIC can be used in either a uni-processor or multi-
processor system.
5.10.1
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through
memory writes on the normal datapath to the processor, and interrupts are handled
without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 can be given a higher priority than
interrupt 3.
• More Interrupts. The I/O APIC in Chipset supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O
APIC devices in the system with their own interrupt vectors.
5.10.2
Interrupt Mapping
The I/O APIC within Chipset supports 24 APIC interrupts. Each interrupt has its own
unique vector assigned by software. The interrupt vectors are mapped as follows, and
match “Config 6” of the Multi-Processor Specification.
120
Datasheet