82NM10 Datasheet, PDF (398/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Table 13-125.RTC (Standard) RAM Bank (LPC I/F—D31:F0)
Index
Name
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh–7Fh
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
Hours Alarm
Day of Week
Day of Month
Month
Year
Register A
Register B
Register C
Register D
114 Bytes of User RAM
13.6.2.1 RTC_REGA—Register A (LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0A
Undefined
No
Attribute:
Size:
Power Well:
R/W
8-bit
RTC
This register is used for general configuration of the RTC functions. None of the bits
are affected by RSMRST# or any other Chipset reset signal.
Bit
Description
7 Update In Progress (UIP) — R/W. This bit may be monitored as a status flag.
0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm
information in RAM is always available when the UIP bit is 0.
1 = The update is soon to occur or is in progress.
6:4 Division Chain Select (DV[2:0]) — R/W. These three bits control the divider chain
for the oscillator, and are not affected by RSMRST# or any other reset signal. DV2
corresponds to bit 6.
010 = Normal Operation
11X = Divider Reset
101 = Bypass 15 stages (test mode only)
100 = Bypass 10 stages (test mode only)
011 = Bypass 5 stages (test mode only)
001 = Invalid
000 = Invalid
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