82NM10 Datasheet, PDF (347/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
31-20 Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the upper 1-MB aligned value (exclusive) of the range. The
incoming address must be less than this value.
19-16 Reserved
15:4
Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the lower 1-MB aligned value (inclusive) of the range. The
incoming address must be greater than or equal to this value.
3:0 Reserved
12.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0)
Offset Address: 24h–27h
Default Value: 00010001h
Attribute:
Size:
R/W, RO
32-bit
Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory
area of the bridge. Accesses that are within the ranges specified in this register will be
sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified
will be accepted by the bridge if CMD.BME is set.
Bit
Description
31-20 Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the upper 1-MB aligned value (exclusive) of the
range. The incoming address must be less than this value.
19-16 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing.
15:4
Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the lower 1-MB aligned value (inclusive) of the
range. The incoming address must be greater than or equal to this value.
3:0 64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing.
12.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 28h–2Bh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0 Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
prefetchable address base.
Datasheet
347