82NM10 Datasheet, PDF (351/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
12.1.21 DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0)
Offset Address: 44h–47h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31 Discard Delayed Transactions (DDT) — R/W.
0 = Logged delayed transactions are kept.
1 = The Chipset PCI bridge will discard any delayed transactions it has logged. This
includes transactions in the pending queue, and any transactions in the active
queue, whether in the hard or soft DT state. The prefetchers will be disabled and
return to an idle state.
NOTE: If a transaction is running on PCI at the time this bit is set, that transaction will
continue until either the PCI master disconnects (by de-asserting FRAME#) or
the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI
bridge when the delayed transaction queues are empty and have returned to an
idle state. Software sets this bit and polls for its completion
30 Block Delayed Transactions (BDT) — R/W.
0 = Delayed transactions accepted
1 = The Chipset PCI bridge will not accept incoming transactions which will result in
delayed transactions. It will blindly retry these cycles by asserting STOP#. All
postable cycles (memory writes) will still be accepted.
29: 8 Reserved
7: 6
Maximum Delayed Transactions (MDT) — R/W. This field controls the maximum
number of delayed transactions that the Chipset PCI bridge will run. Encodings are:
00 =) 2 Active, 5 pending
01 =) 2 active, no pending
10 =) 1 active, no pending
11 =) Reserved
5 Reserved
4 Auto Flush After Disconnect Enable (AFADE) — R/W.
0 = The PCI bridge will retain any fetched data until required to discard by producer/
consumer rules.
1 = The PCI bridge will flush any prefetched data after either the PCI master (by de-
asserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI
transfer.
3 Never Prefetch (NP) — R/W.
0 = Prefetch enabled
1 = The Chipset will only fetch a single DW and will not enable prefetching, regardless
of the command being an Memory read (MR), Memory read line (MRL), or Memory
read multiple (MRM).
Datasheet
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