82NM10 Datasheet, PDF (486/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bits
Description
8 PME Enable (PMEE) — R/W.
0 = Disable.
1 = Enable. SATA controller generates PME# form D3_HOT on a wake event.
7:2 Reserved
1:0 Power State (PS) — R/W. These bits are used both to determine the current power
state of the SATA controller and to set a new power state.
00 = D0 state
11 = D3_HOT state
When in the D3_HOT state, the controller’s configuration space is available, but the I/O
and memory spaces are not. Additionally, interrupts are blocked.
15.1.29 MSICI—Message Signaled Interrupt Capability
Identification (SATA–D31:F2)
Address Offset: 80h–81h
Default Value: 7005h
Attribute:
Size:
RO
16 bits
Bits
Description
15:8
7:0
Next Pointer (NEXT): Indicates the next item in the list is the PCI power management
pointer.
Capability ID (CID): Capabilities ID indicates MSI.
15.1.30 MSIMC—Message Signaled Interrupt Message Control
(SATA–D31:F2)
Address Offset: 82h–83h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bits
Description
15:8 Reserved
7 64 Bit Address Capable (C64): Capable of generating a 32-bit message only.
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