82NM10 Datasheet, PDF (212/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Note:
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh simply aliases to the top of the flash memory.
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
edge of the clock).
• If the device receives a command that is not supported, the device must complete
the cycle gracefully without any impact on the flash content.
• An erase command (page, sector, block, chip, or etc.) must set to 1 (FFh) all bits
inside the designated area (page, sector, block, chip, or etc.).
• Minimum density of 4 Mb (Platform dependent based on size of BIOS).
Chipset only supports Mode 0 on SPI flash devices
5.22.3 Chipset Compatible Command Set
5.22.3.1
Required Command Set for Inter Operability
Table 5-86 contains a list of commands and the associated opcodes that a SPI based
serial flash device must support in order to be interoperable with the serial flash
interface.
Table 5-86.Required Commands and Opcodes
Commands OPCODE
Program Data
02h
Read Data
03h
Read Status
05h
5.22.3.2 Recommended Standard Commands
The following table contains a list of standard commands that a SPI device should
support to be compatible with Chipset. This list only contains standard commands and
is not meant to be an all inclusive list of commands that SPI devices can support.
Table 5-87.Chipset Standard SPI Commands
Commands OPCODE
Notes
Write Status
Write Disable
Write Enable
Fast Read
JEDEC ID
Identify Device
01h
04h
06h
0Bh
9Fh
ABh
If command is supported by a device, 01h must be supported.
If command is supported by a device, 06h must be supported.
Chipset does not support this command.
Either JEDEC ID (9Fh) or an Identify Device with ABh is required,
not both.
Either JEDEC ID (9Fh) or an Identify Device with ABh is required,
not both
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