82NM10 Datasheet, PDF (516/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.3.2.13 PxSACT—Port [1:0] Serial ATA Active (D31:F2)
Address Offset: Port 0: ABAR + 134h
Port 1: ABAR + 1B4h
Attribute:
R/W
Default Value: 00000000h
Size:
32 bits
Bit
Description
31:0
Device Status (DS) — R/W. System software sets this bit for SATA queuing operations
prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared via
the Set Device Bits FIS.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is
cleared by software, and as a result of a COMRESET or SRST.
15.3.2.14 PxCI—Port [1:0] Command Issue Register (D31:F2)
Address Offset: Port 0: ABAR + 138h
Port 1: ABAR + 1B8h
Attribute:
R/W
Default Value: 00000000h
Size:
32 bits
Bit
Description
31:0
Commands Issued (CI) — R/W. This field is set by software to indicate to the Chipset
that a command has been built-in system memory for a command slot and may be sent
to the device. When the Chipset receives a FIS which clears the BSY and DRQ bits for
the command, it clears the corresponding bit in this register for that command slot.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is
cleared by software.
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