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82NM10 Datasheet, PDF (9/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
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11.3
11.2.5 EEPROM_CNTLâEEPROM Control Register
(LAN ControllerâB1:D8:F0) ................................................................... 320
11.2.6 MDI_CNTLâManagement Data Interface (MDI) Control
Register (LAN ControllerâB1:D8:F0)....................................................... 320
11.2.7 REC_DMA_BCâReceive DMA Byte Count Register
(LAN ControllerâB1:D8:F0) ................................................................... 321
11.2.8 EREC_INTRâEarly Receive Interrupt Register
(LAN ControllerâB1:D8:F0) ................................................................... 321
11.2.9 FLOW_CNTLâFlow Control Register
(LAN ControllerâB1:D8:F0) ................................................................... 322
11.2.10PMDRâPower Management Driver Register
(LAN ControllerâB1:D8:F0) ................................................................... 323
11.2.11GENCNTLâGeneral Control Register
(LAN ControllerâB1:D8:F0) ................................................................... 324
11.2.12GENSTAâGeneral Status Register
(LAN ControllerâB1:D8:F0) ................................................................... 324
11.2.13SMB_PCIâSMB via PCI Register
(LAN ControllerâB1:D8:F0) ................................................................... 325
11.2.14Statistical Counters (LAN ControllerâB1:D8:F0) ....................................... 325
ASF Configuration Registers
(LAN ControllerâB1:D8:F0) .............................................................................. 328
11.3.1 ASF_RIDâASF Revision Identification Register
(LAN ControllerâB1:D8:F0) ................................................................... 329
11.3.2 SMB_CNTLâSMBus Control Register
(LAN ControllerâB1:D8:F0) ................................................................... 329
11.3.3 ASF_CNTLâASF Control Register
(LAN ControllerâB1:D8:F0) ................................................................... 330
11.3.4 ASF_CNTL_ENâASF Control Enable Register
(ASF ControllerâB1:D8:F0) ................................................................... 331
11.3.5 ENABLEâEnable Register
(ASF ControllerâB1:D8:F0) ................................................................... 331
11.3.6 APMâAPM Register
(ASF ControllerâB1:D8:F0) ................................................................... 332
11.3.7 WTIM_CONFâWatchdog Timer Configuration Register
(ASF ControllerâB1:D8:F0) ................................................................... 332
11.3.8 HEART_TIMâHeartbeat Timer Register
(ASF ControllerâB1:D8:F0) ................................................................... 333
11.3.9 RETRAN_INTâRetransmission Interval Register
(ASF ControllerâB1:D8:F0) ................................................................... 333
11.3.10RETRAN_PCLâRetransmission Packet Count Limit..................................... 334
11.3.11ASF_WTIM1âASF Watchdog Timer 1 Register
(ASF ControllerâB1:D8:F0) ................................................................... 334
11.3.12ASF_WTIM2âASF Watchdog Timer 2 Register
(ASF ControllerâB1:D8:F0) ................................................................... 334
11.3.13PET_SEQ1âPET Sequence 1 Register
(ASF ControllerâB1:D8:F0) ................................................................... 334
11.3.14PET_SEQ2âPET Sequence 2 Register
(ASF ControllerâB1:D8:F0) ................................................................... 335
11.3.15STAâStatus Register
(ASF ControllerâB1:D8:F0) ................................................................... 335
11.3.16FOR_ACTâForced Actions Register
(ASF ControllerâB1:D8:F0) ................................................................... 336
11.3.17RMCP_SNUMâRMCP Sequence Number Register
(ASF ControllerâB1:D8:F0) ................................................................... 337
Datasheet
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