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82NM10 Datasheet, PDF (621/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
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PCI Express* Configuration Registers
19 PCI Express* Configuration
Registers
19.1
PCI Express* Configuration Registers
(PCI ExpressâD28:F0/F1/F2/F3)
Note:
Register address locations that are not shown in Table 19-148 should be treated as
Reserved.
/
Table 19-148.PCI Express* Configuration Registers Address Map
(PCI ExpressâD28:F0/F1/F2/F3) (Sheet 1 of 3)
Offset Mnemonic
Register Name
00hâ01h
02hâ03h
VID
DID
Vendor Identification
Device Identification
04hâ05h
06hâ07h
08h
PCICMD
PCISTS
RID
PCI Command
PCI Status
Revision Identification
09h
0Ah
0Bh
0Ch
0Dh
0Eh
18hâ1Ah
1Châ1Dh
1Ehâ1Fh
20hâ23h
24hâ27h
28hâ2Bh
2Châ2Fh
34h
3Châ3Dh
3Ehâ3Fh
40hâ41h
42hâ43h
44hâ47h
48hâ49h
4Ahâ4Bh
PI
SCC
BCC
CLS
PLT
HEADTYP
BNUM
IOBL
SSTS
MBL
PMBL
PMBU32
PMLU32
CAPP
INTR
BCTRL
CLIST
XCAP
DCAP
DCTL
DSTS
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Primary Latency Timer
Header Type
Bus Number
I/O Base and Limit
Secondary Status
Memory Base and Limit
Prefetchable Memory Base and Limit
Prefetchable Memory Base Upper 32 Bits
Prefetchable Memory Limit Upper 32 Bits
Capabilities List Pointer
Interrupt Information
Bridge Control
Capabilities List
PCI Express* Capabilities
Device Capabilities
Device Control
Device Status
Function 0â5
Default
8086h
See register
description.
0000h
0010h
See register
description.
00h
04h
06h
00h
00h
81h
000000h
0000h
0000h
00000000h
00010001h
00000000h
00000000h
40h
See bit description
0000h
8010
0041
00000FE0h
0000h
0010h
Type
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
R/W
RO
RO
R/W
R/W, RO
R/WC
R/W
R/W, RO
R/W
R/W
RO
R/W, RO
R/W
RO
R/WO, RO
RO
R/W, RO
R/WC, RO
Datasheet
621
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