82NM10 Datasheet, PDF(263/671 Page) Intel Corporation – Intel® NM10 Family Express Chipset

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82NM10 Datasheet, PDF (263/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

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Register and Memory Mapping

Table 9-109.Memory Decode Ranges from Processor Perspective (Sheet 2 of 2)

Memory Range

512 B anywhere in 64-bit

addressing space

Target

Intel HD Audio Host

Controller

FED0 X000hâFED0 X3FFh

High Precision Event

Timers 3

All other

PCI

Dependency/Comments

Enable via standard PCI mechanism

(Device 30, Function 1)

BIOS determines the âfixedâ location

which is one of four, 1-KB ranges where

X (in the first column) is 0h, 1h, 2h, or

3h.

None

NOTES:

1.

PCI is the target when the Boot BIOS Destination selection bit is low (Chipset Config

Registers:Offset 3401:bit 3). When PCI selected, the Firmware Hub Decode Enable bits

have no effect.

2.

Only LAN cycles can be seen on PCI.

3.

Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High

Precision Event Timers. If attempted, the lock is not honored, which means potential

deadlock conditions may occur.

9.4.1

Boot-Block Update Scheme

The Chipset supports a âtop-block swapâ mode that has the Chipset swap the top block

in the Firmware Hub (the boot block) with another location. This allows for safe update

of the Boot Block (even if a power failure occurs). When the âTOP_SWAPâ Enable bit is

set, the Chipset will invert A16 for cycles targeting Firmware Hub space. When this bit

is 0, the Chipset will not invert A16. This bit is automatically set to 0 by RTCRST#, but

not by PLTRST#.

The scheme is based on the concept that the top block is reserved as the âbootâ block,

and the block immediately below the top block is reserved for doing boot-block

updates.

The algorithm is:

1. Software copies the top block to the block immediately below the top

2. Software checks that the copied block is correct. This could be done by performing

a checksum calculation.

3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the

Firmware Hub. processor access to FFFF_0000h through FFFF_FFFFh will be

directed to FFFE_0000h through FFFE_FFFFh in the Firmware Hub, and processor

accesses to FFFE_0000h through FFFE_FFFF will be directed to FFFF_0000h

through FFFF_FFFFh.

4. Software erases the top block

5. Software writes the new top block

6. Software checks the new top block

7. Software clears the TOP_SWAP bit

8. Software sets the Top_Swap Lock-Down bit

Datasheet

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