82NM10 Datasheet, PDF (267/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
Table 10-110.Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3)
Offset
Mnemonic
Register Name
Default
Type
3414–3414h
3418–341Bh
341C–341Fh
BUC
FD
CG
Backed Up Control
Function Disable
Clock Gating (Netbook Only)
0000001xb
See bit description
00000000h
R/W
R/W, RO
R/W, RO
10.1.1
10.1.2
VCH—Virtual Channel Capability Header Register
Offset Address: 0000–0003h
Default Value: 10010002h
Attribute:
Size:
RO
32-bit
Bit
Description
31:20
19:16
15:0
Next Capability Offset (NCO) — RO.This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates support as a version 1 capability
structure.
Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability
item.
VCAP1—Virtual Channel Capability #1 Register
Offset Address: 0004–0007h
Default Value: 00000801h
Attribute:
Size:
RO
32-bit
Bit
Description
31:12
11:10
9:8
7
6:4
3
2:0
Reserved
Port Arbitration Table Entry Size (PATS) — RO. This field indicates the size of the
port arbitration table is 4 bits (to allow up to 8 ports).
Reference Clock (RC) — RO. Fixed at 100 ns.
Reserved
Low Priority Extended VC Count (LPEVC) — RO. This field indicates that there
are no additional VCs of low priority with extended capabilities.
Reserved
Extended VC Count (EVC) — RO. This field indicates that there is one additional VC
(VC1) that exists with extended capabilities.
Datasheet
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