82NM10 Datasheet, PDF (135/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-53.General Power States for Systems Using Chipset (Sheet 2 of 2)
State/
Substates
Legacy Name / Description
G0/S0/C4
(Netbook
Only)
G1/S1
G1/S3
G1/S4
G2/S5
G3
Stop-Clock with Lower Processor Voltage: This closely resembles the G0/
S0/C3 state. However, after Chipset has asserted STP_CPU#, it then lowers the
voltage to the processor. This reduces the leakage on the processor. Prior to
exiting the C4 state, Chipset increases the voltage to the processor.
Stop-Grant: Similar to G0/S0/C2 state. Chipset also has the option to assert the
CPUSLP# signal to further reduce processor power consumption (Nettop Only).
Note: The behavior for this state is slightly different when supporting iA64
processors.
Suspend-To-RAM (STR): The system context is maintained in system DRAM,
but power is shut off to non-critical circuits. Memory is retained, and refreshes
continue. All clocks stop except RTC clock.
Suspend-To-Disk (STD): The context of the system is maintained on the disk.
All power is then shut off to the system except for the logic required to resume.
Soft Off (SOFF): System context is not maintained. All power is shut off except
for the logic required to restart. A full boot is required when waking.
Mechanical OFF (MOFF): System context not maintained. All power is shut off
except for the RTC. No “Wake” events are possible, because the system does not
have any power. This state occurs if the user removes the batteries, turns off a
mechanical switch, or if the system power supply is at a level that is insufficient
to power the “waking” logic. When system power returns, transition will depends
on the state just prior to the entry to G3 and the AFTERG3 bit in the
GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-61 for more details.
Table 5-54 shows the transitions rules among the various states. Note that transitions
among the various states may appear to temporarily transition through intermediate
states. For example, in going from S0 to S1, it may appear to pass through the G0/S0/
C2 states. These intermediate transitions and states are not listed in the table.
Table 5-54.State Transition Rules for Chipset (Sheet 1 of 2)
Present
State
Transition Trigger
Next State
G0/S0/C0
• Processor halt instruction
• Level 2 Read
• Level 3 Read (Netbook Only)
• Level 4 Read (Netbook Only)
• SLP_EN bit set
• Power Button Override
• Mechanical Off/Power Failure
G0/S0/C1
• Any Enabled Break Event
• STPCLK# goes active
• Power Button Override
• Power Failure
• G0/S0/C1
• G0/S0/C2
• G0/S0/C2, G0/S0/C3 or G0/S0/C4 -
depending on C4onC3_EN bit
(D31:F0:Offset A0h:bit 7) and
BM_STS_ZERO_EN bit (D31:F0:Offset
A9h:bit 2) (Netbook Only)
• G1/Sx or G2/S5 state
• G2/S5
• G3
• G0/S0/C0
• G0/S0/C2
• G2/S5
• G3
Datasheet
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