82NM10 Datasheet, PDF (438/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.9.3
13.9.4
TCO_DAT_OUT—TCO Data Out Register
I/O Address:
Default Value:
Lockable:
TCOBASE +03h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:0 TCO Data Out Value — R/W. This data register field is used for passing commands
from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in
the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL
bits.
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +04h
0000h
No
Attribute:
Size:
Power Well:
R/WC, RO
16-bit
Core
(Except bit 7, in RTC)
Bit
Description
15:13 Reserved
12 DMISERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Chipset received a DMI special cycle message via DMI indicating that it wants to
cause an SERR#. The software must read the (G)MCH/CPU to determine the
reason for the SERR#.
11 Reserved
10 DMISMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Chipset received a DMI special cycle message via DMI indicating that it wants to
cause an SMI. The software must read the (G)MCH/CPU to determine the reason
for the SMI.
9 DMISCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Chipset received a DMI special cycle message via DMI indicating that it wants to
cause an SCI. The software must read the (G)MCH/CPU to determine the reason
for the SCI.
8 BIOSWR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Chipset sets this bit and generates and SMI# to indicate an invalid attempt to write
to the BIOS. This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
b) any write is attempted to the BIOS and the BIOSWP bit is also set.
NOTE: On write cycles attempted to the 4 MB lower alias to the BIOS space, the
BIOSWR_STS will not be set.
438
Datasheet