82NM10 Datasheet, PDF (650/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
7:1 Transaction Class / Virtual Channel Map (TVM) — R/W. This field indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Bit
Transaction Class
7
Transaction Class 7
6
Transaction Class 6
5
Transaction Class 5
4
Transaction Class 4
3
Transaction Class 3
2
Transaction Class 2
1
Transaction Class 1
0
Transaction Class 0
0 Reserved. Transaction class 0 must always be mapped to VC0.
19.1.54 V0STS — Virtual Channel 0 Resource Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 11Ah–11Bh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:2
1
0
Reserved.
VC Negotiation Pending (NP) — RO.
0 = Negotiation is not pending.
1 = Virtual Channel is still being negotiated with ingress ports.
Port Arbitration Tables Status (ATS). There is no port arbitration table for this VC;
this bit is reserved as 0.
19.1.55 UES — Uncorrectable Error Status Register
(PCI Express—D28:F0/F1/F2/F3
Address Offset: 144h–147h
Attribute:
R/WC, RO
Default Value: 00000000000x0xxx0x0x0000000x0000bSize:32 bits
This register maintains its state through a platform reset. It loses its state upon
suspend.
Bit
Description
31:21 Reserved
20 Unsupported Request Error Status (URE) — R/WC.
0 = Unsupported request was Not received.
1 = Unsupported request was received.
19 ECRC Error Status (EE) — RO. ECRC is not supported.
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Datasheet