82NM10 Datasheet, PDF (410/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
3 Popup Mode Enable (PUME) — R/W. When this bit is a 0, the Chipset on Netbook
platform behaves like Chipset, in that bus master traffic is a break event, and it will
return from C3/C4 to C0 based on a break event. See Chapter 5.14.5 for additional
details on this mode.
0 = The Chipset will treat Bus master traffic a break event, and will return from C3/C4
to C0 based on a break event.
1 = When this bit is a 1 and Chipset observes a bus master request, it will take the
system from a C3 or C4 state to a C2 state and auto enable bus masters. This will
let snoops and memory access occur.
2 Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W.
0 = The Chipset sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity
from PCI, PCI Express* and internal bus masters.
1 = When this bit is a 1, Chipset will not set the BM_STS if there is bus master activity
from PCI, PCI Express and internal bus masters.
13.8.1.5
NOTES:
1.
If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the
BM_STS bit will remain set. Software will still need to clear the BM_STS bit.
2.
It is expected that if the PUME bit (this register, bit 3) is set, the
BM_STS_ZERO_EN bit should also be set. Setting one without the other would
mainly be for debug or errata workaround.
3.
BM_STS will be set by LPC DMA (Netbook Only) or LPC masters, even if
BM_STS_ZERO_EN is set.
1:0 Reserved
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Netbook Only)
Offset Address:
Default Value:
Lockable:
Power Well:
AAh
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
This register is used to enable C-state related modes.
Bit
Description
7:4 Reserved
3:2 DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the Chipset
on Netbook platform waits for from the deassertion of DPRSLPVR to the deassertion of
STP_CPU#. This provides a programmable time for the processor’s voltage to stabilize
when exiting from a C4 state. This changes the value for t266.
Bits
00b
01b
10b
11b
t266_min
95 µs
22 µs
34 µs
t266_max
101 µs
28 µs
40 µs
Comment
Default
Value used for “Fast” VRMs
Recommended Value
Reserved
410
Datasheet