82NM10 Datasheet, PDF (464/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
14.2.4
14.2.5
Bit
Description
15:5
4
3
2
1
0
Reserved
Scratchpad (SP) — R/W.
Short Packet Interrupt Enable — R/W.
0 = Disabled.
1 = Enabled.
Interrupt on Complete Enable (IOC) — R/W.
0 = Disabled.
1 = Enabled.
Resume Interrupt Enable — R/W.
0 = Disabled.
1 = Enabled.
Timeout/CRC Interrupt Enable — R/W.
0 = Disabled.
1 = Enabled.
FRNUM—Frame Number Register
I/O Offset:
Word Writes)
Base + (06–07h)Attribute:R/W (Writes must be
Default Value:
0000hSize:16 bits
Bits [10:0] of this register contain the current frame number that is included in the
frame SOF packet. This register reflects the count value of the internal frame number
counter. Bits [9:0] are used to select a particular entry in the Frame List during
scheduled execution. This register is updated at the end of each frame time.
This register must be written as a word. Byte writes are not supported. This register
cannot be written unless the host controller is in the STOPPED state as indicated by the
HCHalted bit (D29:F0/F1/F2/F3:BASE + 02h, bit 5). A write to this register while the
Run/Stop bit is set (D29:F0/F1/F2/F3:BASE + 00h, bit 0) is ignored.
Bit
Description
15:11 Reserved
10:0
Frame List Current Index/Frame Number — R/W. This field provides the frame
number in the SOF Frame. The value in this register increments at the end of each time
frame (approximately every 1 ms). In addition, bits [9:0] are used for the Frame List
current index and correspond to memory address signals [11:2].
FRBASEADD—Frame List Base Address Register
I/O Offset:
Base + (08h–0Bh)Attribute:R/W
Default Value:
UndefinedSize:32 bits
This 32-bit register contains the beginning address of the Frame List in the system
memory. HCD loads this register prior to starting the schedule execution by the host
controller. When written, only the upper 20 bits are used. The lower 12 bits are written
464
Datasheet