82NM10 Datasheet, PDF (113/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
.
Table 5-41.Interrupt Controller Core Connections
8259
8259
Input
Typical Interrupt
Source
Connected Pin / Function
Master
Slave
0
Internal
Internal Timer / Counter 0 output / HPET #0
1
Keyboard
IRQ1 via SERIRQ
2
Internal
Slave controller INTR output
3
Serial Port A
IRQ3 via SERIRQ, PIRQ#
4
Serial Port B
IRQ4 via SERIRQ, PIRQ#
5
Parallel Port / Generic IRQ5 via SERIRQ, PIRQ#
6
Floppy Disk
IRQ6 via SERIRQ, PIRQ#
7
Parallel Port / Generic IRQ7 via SERIRQ, PIRQ#
0
Internal Real Time
Internal RTC / HPET #1
Clock
1
Generic
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
2
Generic
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
3
Generic
IRQ11 via SERIRQ, SCI, TCO, or PIRQ#
4
PS/2 Mouse
IRQ12 via SERIRQ, SCI, TCO, or PIRQ#
5
Internal
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO
interrupt if FERR# not needed.
6
SATA
SATA Primary (legacy mode), or via SERIRQ or
PIRQ#
7
SATA
SATA Secondary (legacy mode) or via SERIRQ or
PIRQ#
Chipset cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for Chipset
PIC.
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,
IRQ8#, and IRQ13.
Note:
Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside Chipset. In the
following descriptions of the 8259s, the interrupt levels are in reference to the signals
at the internal interface of the 8259s, after the required inversions have occurred.
Therefore, the term “high” indicates “active,” which means “low” on an originating
PIRQ#.
Datasheet
113