82NM10 Datasheet, PDF (566/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.2.9
RCV_SLVA—Receive Slave Address Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 09h
Default Value: 44h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
Description
7 Reserved
6:0 SLAVE_ADDR — R/W. This field is the slave address that the Chipset decodes for read
and write cycles. the default is not 0, so the SMBus Slave Interface can respond even
before the processor comes up (or if the processor is dead). This register is cleared by
RSMRST#, but not by PLTRST#.
17.2.10 SLV_DATA—Receive Slave Data Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Ah–0Bh
Default Value: 0000h
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 bits
Resume
This register contains the 16-bit data value written by the external SMBus master. The
processor can then read the value from this register. This register is reset by RSMRST#,
but not PLTRST#
.
Bit
Description
15:8 Data Message Byte 1 (DATA_MSG1) — RO. See Section 5.21.7 - Volume 1 for a
discussion of this field.
7:0 Data Message Byte 0 (DATA_MSG0) — RO. See Section 5.21.7 - Volume 1 for a
discussion of this field.
17.2.11 AUX_STS—Auxiliary Status Register (SMBUS—D31:F3)
Register Offset: SMBASE + 0Ch
Attribute:
R/WC, RO
Default Value: 00h
Size:
8 bits
Lockable:
No
Power Well:
Resume
.
Bit
Description
7:2 Reserved
1 SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible
mode vs. Advanced TCO mode.
0 = Chipset is in the compatible TCO mode.
1 = Chipset is in the advanced TCO mode.
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Datasheet