82NM10 Datasheet, PDF (385/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
3:1 Mode Selection Status — RO. These bits return the counter mode programming. The
binary code returned matches the code used to program the counter mode, as listed
under the bit function above.
000 = Mode 0 — Out signal on end of count (=0)
001 = Mode 1 — Hardware retriggerable one-shot
x10 = Mode 2 — Rate generator (divide by n counter)
x11 = Mode 3 — Square wave output
100 = Mode 4 — Software triggered strobe
101 = Mode 5 — Hardware triggered strobe
0 Countdown Type Status — RO. This bit reflects the current countdown type.
0 = Binary countdown
1 = Binary Coded Decimal (BCD) countdown.
13.3.5
Counter Access Ports Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Counter 0 – 40h,
Counter 1 – 41h,
Counter 2 – 42h
All bits undefined
Attribute:
Size:
R/W
8 bit
Bit
Description
7:0 Counter Port — R/W. Each counter port address is used to program the 16-bit Count
Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is
defined with the Interval Counter Control Register at port 43h. The counter port is also
used to read the current count from the Count Register, and return the status of the
counter programming following a Read Back Command.
13.4
8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0)
13.4.1
Interrupt Controller I/O MAP (LPC I/F—D31:F0)
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers
have multiple functions, depending upon the data written to them. Table 13-121 shows
the different register possibilities for each address.
Table 13-121.PIC Registers (LPC I/F—D31:F0)
Port
Aliases
Register Name
20h
24h, 28h, Master PIC ICW1 Init. Cmd Word 1
2Ch, 30h, _{Master PIC OCW2 Op Ctrl Word 2}
34h, 38h, 3Ch _{Master PIC OCW3 Op Ctrl Word 3}
Default
Value
Undefined
001XXXXXb
X01XXX10b
Type
WO
WO
WO
Datasheet
385