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82NM10 Datasheet, PDF (265/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
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Chipset Configuration Registers
10 Chipset Configuration Registers
This chapter describes all registers and base functionality that is related to chipset
configuration and not a specific interface (e.g., LPC, PCI, or PCI Express*). It contains
the root complex register block that describes the behavior of the upstream internal
link.
This block is mapped into memory space, using register RCBA of the PCI-to-LPC bridge.
Accesses in this space must be limited to 32-(DWord) bit quantities. Burst accesses are
not allowed.
10.1 Chipset Configuration Registers (Memory Space)
Note:
Address locations that are not shown should be treated as Reserved (see Section 9.2
for details).
.
Table 10-110.Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 3)
Offset
Mnemonic
Register Name
Default
Type
0000â0003h
0004â0007h
0008â000Bh
000Câ000Dh
000Eâ000Fh
0010â0013h
0014â0017h
001Aâ001Bh
001Câ001Fh
0020â0023h
0026â0027h
0100â0103h
0104â0107h
0110â0113h
0118â011Fh
0120â0123h
0128â012Fh
VCH
VCAP1
VCAP2
PVC
PVS
V0CAP
V0CTL
V0STS
V1CAP
V1CTL
V1STS
RCTCL
ESD
ULD
ULBA
RP1D
RP1BA
Virtual Channel Capability
Header
Virtual Channel Capability #1
Virtual Channel Capability #2
Port Virtual Channel Control
Port Virtual Channel Status
Virtual Channel 0 Resource
Capability
Virtual Channel 0 Resource
Control
Virtual Channel 0 Resource
Status
Virtual Channel 1 Resource
Capability
Virtual Channel 1 Resource
Control
Virtual Channel 1 Resource
Status
Root Complex Topology
Capability List
Element Self Description
Upstream Link Descriptor
Upstream Link Base Address
Root Port 1 Descriptor
Root Port 1 Base Address
10010002h
00000801h
00000001h
0000h
0000h
00000001h
RO
RO
RO
R/W, RO
RO
RO
800000FFh
R/W, RO
0000h
RO
30008010h
R/WO, RO
00000000h
R/W, RO
0000h
RO
1A010005h
RO
00000602h
00000001h
0000000000000000h
01xx0002h
00000000000E0000h
R/WO, RO
R/WO, RO
R/WO
R/WO, RO
RO
Datasheet
265
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