82NM10 Datasheet, PDF (571/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 17h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:0 DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)
is set to 1.
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Datasheet
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