82NM10 Datasheet, PDF (623/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Table 19-148.PCI Express* Configuration Registers Address Map
(PCI Express—D28:F0/F1/F2/F3) (Sheet 3 of 3)
Offset Mnemonic
Register Name
190h–193h
198h–19Fh
318h
ULD
ULBA
PEETM
Upstream Link Description
Upstream Link Base Address
PCI Express Extended Test Mode Register
Function 0–5
Default
00000001h
See bit description
00h
Type
RO
RO
RO
19.1.1
VID—Vendor Identification Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 00h–01h
Default Value: 8086h
Attribute:
Size:
Bit
Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel
RO
16 bits
19.1.2
DID—Device Identification Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
02h–03h
Port 1= Bit Description
Port 2= Bit Description
Port 3= Bit Description
Port 4= Bit Description
Attribute:
Size:
Bit
Description
15:0 Device ID — RO.
RO
16 bits
19.1.3
PCICMD—PCI Command Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 04h–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11 Reserved
10 Interrupt Disable — R/W. This bit disables pin-based INTx# interrupts on enabled
Hot-Plug and power management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or
power management and MSI is not enabled.
1 = Internal INTx# messages will not be generated.
NOTE: This bit does not affect interrupt forwarding from devices connected to the root
port. Assert_INTx and Deassert_INTx messages will still be forwarded to the
internal interrupt controllers if this bit is set.
9 Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base
Specification.
Datasheet
623