82NM10 Datasheet, PDF (326/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
Table 11-117.ASF Register Address Map
Offset
Mnemonic
Register Name
FDh
FEh
FFh
PMSK6
PMSK7
PMSK8
Polling Mask 6
Polling Mask 7
Polling Mask 8
Default
XXh
XXh
XXh
Type
R/W
R/W
R/W
11.3.1
ASF_RID—ASF Revision Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: E0h
Default Value: ECh
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 ASF ID — RO. Hardwired to 11101 to identify the ASF controller.
2:0 ASF Silicon Revision — RO. This field provides the silicon revision.
11.3.2
SMB_CNTL—SMBus Control Register
(LAN Controller—B1:D8:F0)
Offset Address: E1h
Default Value: 40h
Attribute:
Size:
R/W
8 bits
This register is used to control configurations of the SMBus ports.
Bit
Description
7 SMBus Remote Control ASF Enable (SMB_RCASF) — R/W.
0 = Legacy descriptors and operations are used.
1 = ASF descriptors and operations are used.
6 SMBus ARP Enable (SMB_ARPEN) — R/W.
0 = Disable.
1 = ASF enables the SMBus ARP protocol.
5:4 Reserved
3 SMBus Drive Low (SMB_DRVLO) — R/W.
0 = ASF will not drive the main SMBus signals low while PWR_GOOD = 0.
1 = ASF will drive the main SMBus signals low while PWR_GOOD = 0.
2:0 Reserved
326
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