82NM10 Datasheet, PDF (458/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
14.1.18 USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
C4hAttribute:R/W
Default Value:
00hSize:8 bits
Bit
Description
7:2 Reserved
1 PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/
disconnect events.
0 PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/
disconnect events.
14.1.19 CWP—Core Well Policy Register
(USB—D29:F0/F1/F2/F3)
Address Offset: C8h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:1 Reserved
0 Static Bus Master Status Policy Enable (SBMSPE) — R/W.
0 = The UHCI host controller dynamically sets the Bus Master status bit (Power
Management 1 Status Register,[PMBASE+00h], bit 4) based on the memory
accesses that are scheduled. For Netbook only, the default setting provides a more
accurate indication of snoopable memory accesses in order to help with software-
invoked entry to C3 and C4 power states.
1 = The UHCI host controller statically forces the Bus Master Status bit in power
management space to 1 whenever the HCHalted bit (USB Status Register,
Base+02h, bit 5) is cleared.
NOTE: The PCI Power Management registers are enabled in the PCI Device 31:
Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte
aligned).
14.2
USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub
ports function such that on read back they reflect the current state of the port, and not
necessarily the state of the last write to the register. This allows the software to poll the
state of the port and wait until it is in the proper state before proceeding. A host
controller reset, global reset, or port reset will immediately terminate a transfer on the
affected ports and disable the port. This affects the USBCMD register, bit 4 and the
PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.
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