82NM10 Datasheet, PDF (106/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
If another DMA channel also needs to request a transfer, another sequence can be sent
on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel
3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral
can send the encoded request for channel 3. This allows multiple DMA agents behind an
I/O device to request use of the LPC interface, and the I/O device does not need to self-
arbitrate before sending the message.
Figure 5-11. DMA Request Assertion through LDRQ#
LCLK
LDRQ#
Start
MSB
LSB
ACT
Start
5.7.2
5.7.3
Abandoning DMA Requests
DMA Requests can be deasserted in two fashions: on error conditions by sending an
LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the
DMA transfer. This section describes boundary conditions where the DMA request needs
to be removed prior to a data transfer.
There may be some special cases where the peripheral desires to abandon a DMA
transfer. The most likely case of this occurring is due to a floppy disk controller which
has overrun or underrun its FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was
seen by Chipset, there is no assurance that the cycle has not been granted and will
shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may
still occur. The peripheral can choose not to respond to this cycle, in which case the
host will abort it, or it can choose to complete the cycle normally with any random data.
This method of DMA deassertion should be prevented whenever possible, to limit
boundary conditions both on Chipset and the peripheral.
General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA
transfer is as follows:
1. Chipset starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.
2. Chipset asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.
3. Chipset asserts channel number and, if applicable, terminal count.
4. Chipset indicates the size of the transfer: 8 or 16 bits.
5. If a DMA read -
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Datasheet