82NM10 Datasheet, PDF (277/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.28 LCTL—Link Control Register
Offset Address: 01A8–01A9h
Default Value: 0000h
Attribute:
Size:
R/W
16-bit
Bit
Description
15:8 Reserved
7
Extended Synch (ES) — R/W. When set, this bit forces extended transmission of
FTS ordered sets when exiting L0s prior to entering L0 and extra sequences (Netbook
Only) at exit from L1 prior to entering L0.
6:2 Reserved
1:0
Nettop
Only
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
1:0
Netbook
Only
Active State Link PM Control (APMC) — R/W. This field indicates whether DMI
should enter L0s or L1 or both.
00 = Disabled
01 = L0s entry enabled
10 = L1 Entry enabled
11 = L0s and L1 Entry enabled
10.1.29 LSTS—Link Status Register
Offset Address: 01AA–01ABh
Default Value: 0041h
Attribute:
Size:
RO
16-bit
Bit
Description
15:10
9:4
3:0
Reserved
Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).
Netbook only: The Chipset may also indicate x2 (000010b), depending on CPU
configuration.
Link Speed (LS) — RO. Link is 2.5 Gb/s.
Datasheet
277