82NM10 Datasheet, PDF (121/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-44.APIC Interrupt Mapping
IRQ #¹
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Via
SERIRQ
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
Yes
PIRQA#
PIRQB#
PIRQC#
PIRQD#
N/A
N/A
N/A
N/A
Direct
from Pin
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes³
Yes
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
PIRQH#
Via PCI
Message
Internal Modules
No
Cascade from 8259 #1
Yes
No
8254 Counter 0, HPET #0 (legacy mode)
Yes
Yes
Yes
Yes
Yes
No
RTC, HPET #1 (legacy mode)
Yes
Option for SCI, TCO
Yes
Option for SCI, TCO
Yes
HPET #2, Option for SCI, TCO²
Yes
No
FERR# logic
Yes
SATA Primary (legacy mode)
Yes
SATA Secondary (legacy mode)
Yes
Internal devices are routable; see
Section 10.1.37 though Section 10.1.46.
Yes
Option for SCI, TCO, HPET #0,1,2. Other
internal devices are routable; see
Section 10.1.37 though Section 10.1.46.
NOTES:
1.
When programming the polarity of internal interrupt sources on the APIC, interrupts 0
through 15 receive active-high internal interrupt sources, while interrupts 16 through 23
receive active-low internal interrupt sources.
2.
If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other
devices to ensure the proper operation of HPET #2. Chipset hardware does not prevent
sharing of IRQ 11.
5.10.3
PCI/PCI Express* Message-Based Interrupts
When external devices through PCI / PCI Express wish to generate an interrupt, they
will send the message defined in the PCI Express* Base Specification, Revision 1.0a for
generating INTA# – INTD#. These will be translated internal assertions/de-assertions
of INTA# – INTD#.
Datasheet
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