82NM10 Datasheet, PDF (374/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
8:4
Reserved
3
SATA AHCI Capability— RO:
0 = Capable
1 = Disabled
2:0
Reserved
13.1.34 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bit
Bit
Description
31:14 Base Address (BA) — R/W. Base Address for the root complex register block decode
range. This address is aligned on a 16-KB boundary.
13:1 Reserved
0 Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed
as the Root Complex Register Block.
13.2 DMA I/O Registers (LPC I/F—D31:F0)
Table 13-120.DMA Registers (Sheet 1 of 2)
Port
Alias
Register Name
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
80h
10h
11h
12h
13h
14h
15h
16h
17h
18h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
90h
Channel 0 DMA Base & Current Address
Channel 0 DMA Base & Current Count
Channel 1 DMA Base & Current Address
Channel 1 DMA Base & Current Count
Channel 2 DMA Base & Current Address
Channel 2 DMA Base & Current Count
Channel 3 DMA Base & Current Address
Channel 3 DMA Base & Current Count
Channel 0–3 DMA Command
Channel 0–3 DMA Status
Channel 0–3 DMA Write Single Mask
Channel 0–3 DMA Channel Mode
Channel 0–3 DMA Clear Byte Pointer
Channel 0–3 DMA Master Clear
Channel 0–3 DMA Clear Mask
Channel 0–3 DMA Write All Mask
Reserved Page
Default Type
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
000001XXb
000000XXb
Undefined
Undefined
Undefined
0Fh
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
RO
WO
WO
WO
WO
WO
R/W
R/W
374
Datasheet