82NM10 Datasheet, PDF (620/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.2.43 SDBDPL—Stream Descriptor Buffer Descriptor List Pointer
Lower Base Address Register
(Intel HD Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 98hAttribute:
Input Stream[1]: HDBAR + B8h
Input Stream[2]: HDBAR + D8h
Input Stream[3]: HDBAR + F8h
Output Stream[0]: HDBAR + 118h
Output Stream[1]: HDBAR + 138h
Output Stream[2]: HDBAR + 158h
Output Stream[3]: HDBAR + 178h
R/W,RO
Default Value:
00000000hSize:32 bits
Bit
Description
31:7
6:0
Buffer Descriptor List Pointer Lower Base Address — R/W. This field is the lower
address of the Buffer Descriptor List. This value should only be modified when the RUN
bit is 0, or DMA transfer may be corrupted.
Hardwired to 0 forcing alignment on 128-B boundaries.
18.2.44 SDBDPU—Stream Descriptor Buffer Descriptor List Pointer
Upper Base Address Register (Intel HD Audio Controller—
D27:F0)
Memory Address:Input Stream[0]: HDBAR + 9ChAttribute:
Input Stream[1]: HDBAR + BCh
Input Stream[2]: HDBAR + DCh
Input Stream[3]: HDBAR + FCh
Output Stream[0]: HDBAR + 11Ch
Output Stream[1]: HDBAR + 13Ch
Output Stream[2]: HDBAR + 15Ch
Output Stream[3]: HDBAR + 17Ch
R/W
Default Value:
00000000hSize:32 bits
Bit
Description
31:0
Buffer Descriptor List Pointer Upper Base Address — R/W. This field is the upper
32-bit address of the Buffer Descriptor List. This value should only be modified when
the RUN bit is 0, or DMA transfer may be corrupted.
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