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82NM10 Datasheet, PDF (13/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset | |||
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13.5.2 INDâIndex Register (LPC I/FâD31:F0)................................................... 395
13.5.3 DATâData Register (LPC I/FâD31:F0).................................................... 395
13.5.4 EOIRâEOI Register (LPC I/FâD31:F0) .................................................... 395
13.5.5 IDâIdentification Register (LPC I/FâD31:F0)........................................... 396
13.5.6 VERâVersion Register (LPC I/FâD31:F0) ................................................ 396
13.5.7 REDIR_TBLâRedirection Table (LPC I/FâD31:F0)..................................... 397
13.6 Real Time Clock Registers (LPC I/FâD31:F0) ...................................................... 399
13.6.1 I/O Register Address Map (LPC I/FâD31:F0)............................................ 399
13.6.2 Indexed Registers (LPC I/FâD31:F0) ...................................................... 399
13.7 Processor Interface Registers (LPC I/FâD31:F0).................................................. 403
13.7.1 NMI_SCâNMI Status and Control Register
(LPC I/FâD31:F0) ................................................................................ 404
13.7.2 NMI_ENâNMI Enable (and Real Time Clock Index)
Register (LPC I/FâD31:F0).................................................................... 405
13.7.3 PORT92âFast A20 and Init Register (LPC I/FâD31:F0) ............................. 405
13.7.4 COPROC_ERRâCoprocessor Error Register
(LPC I/FâD31:F0) ................................................................................ 405
13.7.5 RST_CNTâReset Control Register (LPC I/FâD31:F0) ................................ 406
13.8 Power Management Registers (PMâD31:F0) ....................................................... 406
13.8.1 Power Management PCI Configuration Registers
(PMâD31:F0) ...................................................................................... 406
13.8.2 APM I/O Decode ................................................................................... 415
13.8.3 Power Management I/O Registers ........................................................... 415
13.9 System Management TCO Registers (D31:F0) ..................................................... 438
13.9.1 TCO_RLDâTCO Timer Reload and Current Value Register .......................... 439
13.9.2 TCO_DAT_INâTCO Data In Register ....................................................... 439
13.9.3 TCO_DAT_OUTâTCO Data Out Register .................................................. 440
13.9.4 TCO1_STSâTCO1 Status Register .......................................................... 440
13.9.5 TCO2_STSâTCO2 Status Register .......................................................... 442
13.9.6 TCO1_CNTâTCO1 Control Register ......................................................... 443
13.9.7 TCO2_CNTâTCO2 Control Register ......................................................... 443
13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................... 444
13.9.9 TCO_WDCNTâTCO Watchdog Control Register ......................................... 444
13.9.10SW_IRQ_GENâSoftware IRQ Generation Register .................................... 445
13.9.11TCO_TMRâTCO Timer Initial Value Register ............................................. 445
13.10 General Purpose I/O Registers (D31:F0) ............................................................. 445
13.10.1GPIO_USE_SELâGPIO Use Select Register .............................................. 446
13.10.2GP_IO_SELâGPIO Input/Output Select Register ....................................... 447
13.10.3GP_LVLâGPIO Level for Input or Output Register ..................................... 447
13.10.4GPO_BLINKâGPO Blink Enable Register .................................................. 447
13.10.5GPI_INVâGPIO Signal Invert Register..................................................... 448
13.10.6GPIO_USE_SEL2âGPIO Use Select 2 Register[63:32] ............................... 448
13.10.7GP_IO_SEL2âGPIO Input/Output Select 2 Register[63:32] ........................ 449
13.10.8GP_LVL2âGPIO Level for Input or Output 2 Register[63:32] ...................... 449
14 UHCI Controllers Registers .................................................................................... 450
14.1
PCI Configuration Registers
(USBâD29:F0/F1/F2/F3).................................................................................. 450
14.1.1 VIDâVendor Identification Register
(USBâD29:F0/F1/F2/F3) ...................................................................... 451
14.1.2 DIDâDevice Identification Register
(USBâD29:F0/F1/F2/F3) ...................................................................... 451
14.1.3 PCICMDâPCI Command Register (USBâD29:F0/F1/F2/F3)........................ 451
Datasheet
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