82NM10 Datasheet, PDF (655/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.61 RES — Root Error Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 170h–173h
Default Value: 00000000h
Attribute:
Size:
R/WC, RO
32 bits
Bit
Description
31:27 Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error
interrupt allocated.
26:4 Reserved
3 Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Chipset, only one
error will be captured.
2 ERR_FATAL/NONFATAL Received (ENR) — R/WC.
0 = No error message received.
1 = Either a fatal or a non-fatal error message is received.
1 Multiple ERR_COR Received (MCR) — RO. For Chipset, only one error will be
captured.
0 ERR_COR Received (CR) — R/WC.
0 = No error message received.
1 = A correctable error message is received.
19.1.62 RCTCL — Root Complex Topology Capability List Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 180–183h
Default Value: 00010005h
Attribute:
Size:
RO
32 bits
Bit
Description
31:20 Next Capability (NEXT) — RO. This field indicates the next item in the list, in this
case, end of list.
19:16 Capability Version (CV) — RO. This field indicates the version of the capability
structure.
15:0 Capability ID (CID) — RO. This field indicates this is a root complex topology
capability.
Datasheet
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